IBIS Macromodel Task Group Meeting date: 20 Sep 2011 Members (asterisk for those attending): Agilent: Fangyi Rao * Radek Biernacki Altera: * David Banas Ansys: Samuel Mertens * Dan Dvorscak * Curtis Clark Arrow Electronics: Ian Dodd Cadence Design Systems: Terry Jernberg * Ambrish Varma Celsionix: Kellee Crisafulli Cisco Systems: Ashwin Vasudevan Syed Huq Ericsson: Anders Ekholm IBM: * Greg Edlund Intel: Michael Mirmak LSI Logic: Wenyi Jin Mentor Graphics: * John Angulo Zhen Mu * Arpad Muranyi Vladimir Dmitriev-Zdorov Micron Technology: Randy Wolff NetLogic Microsystems: Ryan Couts Nokia-Siemens Networks: * Eckhard Lenski QLogic Corp. * James Zhou Sigrity: Brad Brim Kumar Keshavan Ken Willis SiSoft: * Walter Katz * Todd Westerhoff Doug Burns Snowbush IP: Marcus Van Ierssel ST Micro: Syed Sadeghi Teraspeed Consulting Group: Scott McMorrow * Bob Ross TI: Casey Morrison Alfred Chong Vitesse Semiconductor: Eric Sweetman Xilinx: Mustansir Fanaswalla unaffiliated: * Mike LaBonte The meeting was lead by Todd Westerhoff ------------------------------------------------------------------------ Opens: - None -------------------------- Call for patent disclosure: - None ------------- Review of ARs: - Walter update BIRD 123.2.4 and send to Mike for posting - In progress ------------- New Discussion: Todd showed a presentation from Greg: - Slide 2: - Greg: Should we keep the terminator block on slide 2? - Walter: We should not - David: Does that mean not series pin in a TX model? - Walter: Sometimes people add a termination to the buffer - But it's really part of the buffer model - David: It would be good to have terminator options instead of several buffers - Bob: One way to have terminations is through sub-models - Todd: We usually need diff termination - IBIS [Model] declarations are single ended - Slide 3: - Greg: The simulated PLL and CDR will model RX jitter - Walter: This is accurate for stat - For time domain CDR is in the ALG box - Getwave usually does not have CDR in it - Don't know if this is output or input to EQ2 - Kumar and Ambrish needed the files, no web client running - Walter: We have a RX model of type Terminator - Radek: That should be allowed - Todd: If clock_ticks are not provided by the model, RX Clock_Recovery params are used to provide a clock budget - The main question is what point in the circuit jitter is injected - Discussion of which parameters go where - David: Why no TX voltage noise parameters? - What protection would there be against disclosing jitter specifics? - Is TX Rj from EDA tool to model or vice-versa? - Is it from the user or from the model? - Walter: It is from the model - Kumar: RX Sj is modeled at the CDR - The EDA tool should not add Sj - David: How are refclk imperfections modeled? - Todd: TX Rj is an Info param - In the current BIRD the model is not expected to do anything with RX Sj - It never sees the param - BIRD 123 is about the EDA tool modulating clock_ticks - Walter: When CDR does not include RX Sj DCD on refclk CDR ??? - If RX Sj is modeled in the algorithmic model's CDR it should not be an info param - Todd: New params can be created to tell the model how much Sj to generate - Walter: It would have a new name, Model_Specific - Todd: Does the simulator use only Info parameters? - What if the DLL accepts an Input Rx_Sj parameter? - Walter: It would be confusing if we overloaded that - Arpad: The spec doesn't say that can't be done - Mike: Slides 2 & 3 should have the jitter params annotated at the right places Walter showed an email to explain Sj in BIRD 123.2.5: - David: We need to specify this at multiple frequencies - Walter: Fangyi brought that up - A new BIRD would be needed for that - Kumar: Would multiple instances of Sj do it? - Walter: We would need something like a separate file or PDF - Dual-Dirac has just 2 points - In statistical mode a clock PDF might be adjusted - David: Is it guaranteed simulators will observe clock_ticks? - Walter: Yes - Todd: Is there a difference between the simulator and the DLL modulating Sj? - Kumar: The simulator will be more pessimistic - The DLL will remove it - Walter: At high freq the model might ask the EDA tool to do it - Todd: Injecting at the latch and refclk are different - Kumar: If the tool does the jittering it can't be tracked - Walter: BUJ is jitter than the DLL can't model - But it needs to be incorporated into the final result - David: Why defend the request to the EDA tool to add jitter? - Kumar: Often the CDR tracks jitter and takes it out - Todd: It helps to know the physical basis of these jitters - Power supply noise will not track out - Walter: Anything that can't be tracked should be disclosed - Todd: Is frequency required if RX Sj is specified? - David: How is a simple magnitude of Sj helpful? - That depends on how much goes into the CDR - Walter: This is spread across all frequencies - David; No CDR has a white noise jitter function - Walter: It's a budget, which distribution should it be? - We had discussed whether these should be Info or Out - Amplitude noise changes with time where AGC is used Meeting ended. ------------- Next meeting: 27 Sep 2011 12:00pm PT Next agenda: 1) Task list item discussions ------------- IBIS Interconnect SPICE Wish List: 1) Simulator directives